After Silicon: The Technologies That Will Power the Next Era of Computing
After Silicon: The Technologies That Will Power the Next Era of Computing
后硅时代：驱动下一代计算的变革性技术
From atomic-scale transistors to chips made of light — here is what comes after the 2nm revolution, and why it matters for everything from your smartphone to artificial general intelligence.
从原子级晶体管到光子芯片——以下是 2nm 革命之后的未来技术，以及它们为何对从智能手机到通用人工智能的一切领域至关重要。
In Q4 2025, TSMC confirmed volume production of its N2 node. At 2nm, transistor gates are approximately 10 silicon atoms wide. That is not a metaphor for “very small” — it is a regime where quantum tunnelling, variability at the atomic scale, and statistical dopant fluctuations are no longer edge cases. They are the design constraints. The engineering community has spent decades treating Moore’s Law as a roadmap. What comes next is not one road. It is six, running in parallel.
2025 年第四季度，台积电（TSMC）确认了其 N2 工艺节点的量产。在 2nm 尺度下，晶体管栅极的宽度大约仅相当于 10 个硅原子。这并非形容“非常小”，而是进入了一个量子隧穿效应、原子级变异性以及统计掺杂波动不再是边缘情况，而是必须面对的设计约束的领域。工程界几十年来一直将摩尔定律视为路线图，但接下来的发展不再是一条路，而是六条并行之路。
1. Gate-All-Around (GAA) Transistors
1. 全环绕栅极（GAA）晶体管
FinFETs gave the gate three sides of control over the channel. GAA wraps it around all four sides of horizontally stacked silicon nanosheets — typically 5–8 ribbons, each 5nm thick, separated by high-k dielectric. The physics: improved electrostatic gate control means steeper subthreshold slope, lower off-state leakage current (I_off), and the ability to tune drive current (I_on) by adjusting nanosheet width at the mask level — something FinFETs could not do without a full process change.
FinFET 结构让栅极能够从三个侧面控制沟道，而 GAA 则将栅极包裹在水平堆叠的硅纳米片（通常为 5-8 层，每层 5nm 厚，由高 k 电介质隔开）的所有四个侧面上。其物理优势在于：改进的静电栅极控制意味着更陡峭的亚阈值摆幅、更低的关断漏电流（I_off），并且可以通过在掩模层级调整纳米片宽度来调节驱动电流（I_on）——这是 FinFET 在不彻底改变工艺流程的情况下无法做到的。
TSMC N2: 10–15% speed gain at iso-power, or 25–30% power reduction at iso-performance vs N3E. Gate pitch ~45nm, metal pitch ~24nm. Intel 18A: Combines RibbonFET (GAA) with Backside Power Delivery Network (BSPDN) — PowerVia. Routing Vdd and Vss on the back of the wafer eliminates IR drop from power rails competing with signal routing on the front. Result: ~6% performance gain from BSPDN alone, plus freed routing tracks for signal density.
台积电 N2 工艺：与 N3E 相比，在同等功耗下速度提升 10-15%，或在同等性能下功耗降低 25-30%。栅极间距约为 45nm，金属间距约为 24nm。英特尔 18A 工艺：将 RibbonFET（GAA）与背面供电网络（BSPDN，即 PowerVia）相结合。通过在晶圆背面布设 Vdd 和 Vss 电源线，消除了电源线与正面信号布线竞争导致的电压降（IR drop）。结果：仅 BSPDN 一项就带来了约 6% 的性能提升，并释放了布线轨道以提高信号密度。
2. 3D Integration: Chiplets and Hybrid Bonding
2. 3D 集成：芯粒（Chiplets）与混合键合
Monolithic scaling hits yield walls fast — defect density is roughly constant per unit area, so doubling die area roughly halves yield. Chiplets solve this by partitioning a design into smaller dies, each manufactured at the process node best suited to it, then integrated in-package. The future AI accelerator likely stacks a logic die (leading-edge node), HBM (DRAM-optimised node), and a photonics die (specialised process) — heterogeneous integration as the norm.
单片集成缩放很快会触及良率瓶颈——缺陷密度在单位面积上大致恒定，因此芯片面积翻倍会导致良率减半。芯粒技术通过将设计划分为更小的芯片来解决这一问题，每个芯片采用最适合的工艺节点制造，然后在封装内集成。未来的 AI 加速器很可能会堆叠逻辑芯片（采用尖端工艺）、HBM（采用 DRAM 优化工艺）和光子芯片（采用专用工艺）——异构集成将成为常态。
3. Silicon Photonics and Co-Packaged Optics
3. 硅光子学与共封装光学（CPO）
The bandwidth-per-watt of copper interconnects degrades sharply beyond ~1–2m. At rack scale in AI clusters, this is the bottleneck — not the GPU. Silicon photonics builds optical components on standard 300mm CMOS wafers. Co-Packaged Optics (CPO) eliminates the pluggable transceiver entirely — the optical engine is wire-bonded or hybrid-bonded directly to the switch ASIC. Nvidia’s Quantum-X800 and Spectrum-X800 use CPO at 100–400 Tb/s aggregate, with 3.5x power efficiency improvement and 10x signal integrity improvement vs pluggable modules.
铜互连的单位功耗带宽在超过 1-2 米后会急剧下降。在 AI 集群的机架规模下，这是瓶颈所在，而非 GPU 本身。硅光子学在标准的 300mm CMOS 晶圆上构建光学组件。共封装光学（CPO）彻底消除了可插拔收发器——光学引擎通过引线键合或混合键合直接连接到交换机 ASIC 上。英伟达的 Quantum-X800 和 Spectrum-X800 采用了 CPO 技术，总带宽达到 100-400 Tb/s，与可插拔模块相比，能效提升了 3.5 倍，信号完整性提升了 10 倍。
4. Wide-Bandgap Semiconductors: GaN and SiC
4. 宽禁带半导体：氮化镓（GaN）与碳化硅（SiC）
Wide-bandgap materials change the limits of breakdown voltage, thermal conductivity, and electron saturation velocity. GaN exploits a 2D electron gas (2DEG) at the AlGaN/GaN heterojunction — a high-density, high-mobility channel that enables HEMT transistors switching at RF frequencies and power conversion at >90% efficiency. SiC MOSFETs handle 650V–3.3kV switching for EV traction inverters, industrial motor drives, and grid infrastructure. SiC inverter switching losses are ~50% lower than equivalent silicon IGBTs.
宽禁带材料改变了击穿电压、热导率和电子饱和速度的极限。氮化镓（GaN）利用 AlGaN/GaN 异质结处的二维电子气（2DEG）——这是一种高密度、高迁移率的沟道，使 HEMT 晶体管能够在射频频率下切换，并实现超过 90% 的功率转换效率。碳化硅（SiC）MOSFET 则处理 650V-3.3kV 的开关任务，用于电动汽车牵引逆变器、工业电机驱动和电网基础设施。SiC 逆变器的开关损耗比同类硅基 IGBT 低约 50%。
5. 2D Materials: Graphene and TMDs
5. 二维材料：石墨烯与过渡金属硫族化合物（TMDs）
The IEEE roadmap identifies 2D materials as the primary candidate for sub-1nm channel materials. Graphene’s electron mobility makes it exceptional for interconnects; Graphene interconnects show 100x higher current density than copper at equivalent dimensions. TMDs (MoS₂, WSe₂, WS₂) are semiconducting 2D materials with bandgaps of 1.0–2.0 eV at monolayer thickness. TSMC’s research division has demonstrated stacked nanosheet GAA transistors with these materials.
IEEE 路线图将二维材料确定为 1nm 以下沟道材料的主要候选者。石墨烯的电子迁移率使其成为互连的绝佳选择；在同等尺寸下，石墨烯互连的电流密度比铜高出 100 倍。TMDs（如 MoS₂、WSe₂、WS₂）是半导体二维材料，在单层厚度下具有 1.0-2.0 eV 的带隙。台积电研究部门已经展示了使用这些材料堆叠的纳米片 GAA 晶体管。