IBM has unveiled chip technology that could help extend Moore’s Law another decade
IBM has unveiled chip technology that could help extend Moore’s Law another decade
IBM 发布了有望将摩尔定律再延长十年的芯片技术
EXECUTIVE SUMMARY IBM has built a new prototype chip with around 100 billion transistors on an area the size of a fingernail, which is twice the density of the company’s previous state-of-the-art technology announced in 2021. The design could pave the way for faster and more energy efficient computers for years to come.
执行摘要 IBM 制造出了一款新的原型芯片，在指甲盖大小的面积上集成了约 1000 亿个晶体管，其密度是该公司 2021 年公布的上一代顶尖技术的两倍。这一设计有望为未来多年更快速、更节能的计算机铺平道路。
For more than half a century, chipmakers have been able to make ever more powerful computers by following the key principle of Moore’s Law: Cram more transistors onto the chip. To do this, they shrank transistors—the tiny switches that perform computations—to incrementally smaller sizes. But in the last 15 years, transistors have gotten close to the point where quantum mechanics starts to interfere with their function: just a few dozen nanometers in size. They can’t get smaller. So to fit more transistors on a chip, engineers across the industry are eyeing a pivot to an approach familiar to urban planners: build up.
半个多世纪以来，芯片制造商一直遵循摩尔定律的核心原则，即在芯片上塞入更多的晶体管，从而制造出功能越来越强大的计算机。为了实现这一点，他们不断缩小晶体管（执行计算的微小开关）的尺寸。但在过去 15 年里，晶体管的尺寸已接近量子力学开始干扰其功能的临界点：仅有几十纳米大小。它们已无法再缩小。因此，为了在芯片上容纳更多晶体管，整个行业的工程师们正着眼于转向一种城市规划者所熟悉的方法：向上建造。
On Thursday, IBM announced it has created a chip that uses this strategy. The new architecture, known as a nanostack, vertically stacks transistors in two layers on a silicon chip. “It’s not just an incremental step,” Jay Gambetta, the director of IBM Research, said during a press conference on Tuesday. “It’s a meaningful leap forward.”
周四，IBM 宣布已开发出一种采用该策略的芯片。这种被称为“纳米堆叠”（nanostack）的新架构在硅芯片上垂直堆叠了两层晶体管。IBM 研究院院长 Jay Gambetta 在周二的新闻发布会上表示：“这不仅仅是渐进式的一步，而是一个意义重大的飞跃。”
Within a decade, Gambetta expects, chips with nanostacking will be widely used in data centers, where their improved efficiency could help the facilities better manage their energy consumption. “Absolutely, it’s transformational,” says Dan Hutcheson, vice chair of TechInsights, a technology analysis company. “This puts another 10, 15 years on the roadmap.”
Gambetta 预计，十年内，采用纳米堆叠技术的芯片将广泛应用于数据中心，其更高的效率将有助于这些设施更好地管理能源消耗。技术分析公司 TechInsights 副主席 Dan Hutcheson 表示：“这绝对是变革性的。它为技术路线图又延长了 10 到 15 年。”
Compared with IBM’s previous state-of-the-art architecture, the company reports, chips built with this new approach can do as much as 50% more work in the same amount of time and be up to 70% more energy efficient. The architecture offers a general way of laying out transistors, and IBM will partner with semiconductor manufacturers to make the actual chips. It anticipates that chip designers will deploy the design in many different types of chips, including GPUs and CPUs.
据 IBM 报告，与该公司之前的顶尖架构相比，采用这种新方法制造的芯片在相同时间内的工作效率可提高多达 50%，能效则可提升高达 70%。该架构提供了一种通用的晶体管布局方式，IBM 将与半导体制造商合作生产实际芯片。该公司预计，芯片设计师将在包括 GPU 和 CPU 在内的多种芯片中部署该设计。
“I expect to have many conversations with conversations with designers about how they can use this technology,” Huiming Bu, IBM’s vice president of global semiconductor R&D, said in the press conference announcing the new design.
IBM 全球半导体研发副总裁 Huiming Bu 在宣布该新设计的新闻发布会上表示：“我期待与设计师们进行深入交流，探讨他们如何利用这项技术。”
A layer cake Engineers created IBM’s new chip layer by layer, like a cake. They start by fabricating transistors on one layer of silicon. Then they place a silicon layer on top of these devices, and they fabricate another layer of transistors directly on top of that. Finally, they create the electrical connections between the two layers of transistors. This kind of vertical stack, which combines two types of transistors, is known as a complementary field-effect transistor, or CFET, explains Qing Cao, a professor of materials science and engineering at the University of Illinois at Urbana-Champaign, who was not involved with the work.
层叠蛋糕 工程师们像制作蛋糕一样，一层一层地制造了 IBM 的这款新芯片。他们首先在一层硅片上制造晶体管，然后在这些器件上方放置一层硅，并直接在其上制造另一层晶体管。最后，他们在两层晶体管之间建立电气连接。伊利诺伊大学厄巴纳-香槟分校材料科学与工程教授 Qing Cao（未参与此项工作）解释说，这种结合了两种晶体管的垂直堆叠方式被称为互补场效应晶体管（CFET）。
The company isn’t the only one pursuing this general approach. The biggest chip manufacturers—Intel, Samsung, and TSMC—and the competing research lab Imec in Belgium have been investigating CFETs. IBM says its design is distinguished by the fact that the transistors in the second layer do not sit directly on top of the first layer’s transistors; rather, they are staggered, which the company says simplifies wiring, among other advantages.
并非只有 IBM 在探索这一通用方法。英特尔、三星和台积电等大型芯片制造商，以及比利时的竞争研究实验室 Imec，也一直在研究 CFET。IBM 表示，其设计的独特之处在于，第二层的晶体管并非直接位于第一层晶体管的正上方，而是采用了交错排列，该公司称这简化了布线并带来了其他优势。
CFETs like those in IBM’s nanostack architecture contrast with another common approach to making two-tiered chips, such as AMD’s 3D V-Cache and Huawei’s forthcoming LogicFolding technology, Cao says. In those approaches, engineers fabricate the transistors on each layer of the chip independently before bonding the two together. IBM’s new method allows for more precise alignment of the layers, which is important for performance because transistors are so tiny, says Cao.
Cao 指出，像 IBM 纳米堆叠架构中的这类 CFET，与制造双层芯片的另一种常见方法（如 AMD 的 3D V-Cache 和华为即将推出的 LogicFolding 技术）形成了对比。在那些方法中，工程师是在将两层芯片键合在一起之前，分别独立制造每一层的晶体管。Cao 表示，IBM 的新方法允许更精确的层间对齐，由于晶体管极其微小，这对性能至关重要。
Nanostacking builds on an approach called nanosheet technology, which has been used to make current state-of-the-art transistors since around 2022. A transistor is essentially a hose through which electrons flow, with a valve that can turn the flow on or off. Inside the transistor, electrons move through a patch of the silicon called a channel. In IBM’s nanostack approach, the channel consists of three nanosheets that are each 15 atoms thick, spaced nine nanometers apart.
纳米堆叠技术建立在一种称为“纳米片”（nanosheet）的技术之上，该技术自 2022 年左右起就被用于制造当前的顶尖晶体管。晶体管本质上是一根电子流过的软管，配有一个可以开启或关闭电流的阀门。在晶体管内部，电子通过一块称为“沟道”的硅片区域。在 IBM 的纳米堆叠方法中，沟道由三片纳米片组成，每片厚度为 15 个原子，间距为 9 纳米。
Every chip generation gets a name. IBM refers to its nanostack technology as “sub-nanometer” or “0.7 nanometer,” following a longtime industry convention where each generation is named for a smaller and smaller length. But “0.7 nanometer” is a marketing term and does not correspond to any physical characteristics of the chip. The distance between transistors “has been staying at about 40 nanometers for quite a long period of time,” says Cao.
每一代芯片都有一个名称。IBM 将其纳米堆叠技术称为“亚纳米”或“0.7 纳米”，遵循了行业长期以来的惯例，即每一代产品的命名都对应越来越小的长度。但“0.7 纳米”是一个营销术语，并不对应芯片的任何物理特性。Cao 指出，晶体管之间的距离“在很长一段时间内一直保持在 40 纳米左右”。
Putting it into production Looking ahead, chipmakers can try increasing transistor density by building on more tiers, as Bu suggested in the press conference. However, they will face practical challenges, according to Cao. Manufacturing introduces errors, which means a certain number of chips are faulty upon creation. “Here you’re building another layer on top, so if either top layer or bottom layer fail, your entire chip is going to fail,” says Cao. The resulting failure rate will be higher than for single-layer chips, and that will be costly.
投入生产 展望未来，正如 Bu 在新闻发布会上所暗示的那样，芯片制造商可以尝试通过增加更多层数来提高晶体管密度。然而，据 Cao 称，他们将面临实际挑战。制造过程会引入误差，这意味着一定数量的芯片在生产时就会出现故障。Cao 说：“在这里，你在上面又建了一层，所以如果顶层或底层出现故障，整个芯片就会报废。”由此产生的故障率将高于单层芯片，这将带来高昂的成本。
Another central challenge is what Cao calls “the thermal budget.” Essentially, it means that engineers need to figure out how to build each layer without melting the connections to the one underneath. This means keeping manufacturing processes below 400 °C. IBM figured out how to make the second stack at low enough temperature, although the company is mum about its methods. Academics are also on the case. Cao’s group, for example, has created a method for stacking transistors layer by layer where the second layer is created with processes below 200 °C. They manage this by using a type of transistor known as the junctionless transistor.
另一个核心挑战是 Cao 所说的“热预算”。本质上，这意味着工程师需要设法在不熔化下方连接的情况下构建每一层。这意味着制造过程必须保持在 400°C 以下。IBM 已经找到了在足够低的温度下制造第二层堆叠的方法，尽管该公司对具体方法守口如瓶。学术界也在研究这个问题。例如，Cao 的团队创造了一种逐层堆叠晶体管的方法，其中第二层是在低于 200°C 的工艺下制造的。他们通过使用一种称为“无结晶体管”（junctionless transistor）的器件实现了这一点。