What "Memory Compiler" Actually Means: From Bitcells to GDS Tiling
What “Memory Compiler” Actually Means: From Bitcells to GDS Tiling
“内存编译器”的真正含义：从位单元到 GDS 平铺
May 29, 2026 [compiler-design] #memory-compiler #sram #eda #layout-vs-schematic #tiling 2026年5月29日 [编译器设计] #内存编译器 #SRAM #EDA #版图与原理图一致性 #平铺
Most people see the name “memory compiler” and have no idea what it actually does. 大多数人看到“内存编译器”（Memory Compiler）这个名字时，并不知道它到底是做什么的。
1. Compiler Representation
1. 编译器的表示法
The classical representation is the T-diagram (or Tombstone diagram). It characterizes a compiler by three languages: the source language it reads (A), the target language it emits (B), and the implementation language it is written in (C): 经典的表示法是 T 型图（或墓碑图）。它通过三种语言来表征一个编译器：它读取的源语言 (A)、它输出的目标语言 (B) 以及它所使用的实现语言 (C)：
┌───┬───┐
│ A → B │
└───┴───┘
│ CRead it as: “a program that translates A into B, written in C.” 可以这样解读：“一个用 C 语言编写的、将 A 翻译成 B 的程序。”
The textbook example is C → machine code. But the definition is broader than that: 教科书式的例子是 C 语言 → 机器码。但其定义远不止于此：
- Typical compiler: C / C++ → assembly / machine code
- 典型编译器： C / C++ → 汇编 / 机器码
- The compiler I work on at Synopsys: VHDL / Verilog RTL → simulation / debugging database
- 我在 Synopsys 负责的编译器： VHDL / Verilog RTL → 仿真 / 调试数据库
- Memory compiler: design parameters (depth, width, port…) → all views needed to tape out a chip
- 内存编译器： 设计参数（深度、宽度、端口等） → 芯片流片所需的所有视图
- Shader compiler: GLSL / HLSL → GPU machine code (e.g., Mesa’s NIR pipeline, DXC)
- 着色器编译器： GLSL / HLSL → GPU 机器码（例如 Mesa 的 NIR 流水线、DXC）
- Query compiler: SQL → a physical execution plan (e.g., PostgreSQL’s planner/executor)
- 查询编译器： SQL → 物理执行计划（例如 PostgreSQL 的规划器/执行器）
- Bytecode compiler: Java source → JVM bytecode (javac), or JavaScript → V8 bytecode (Ignition)
- 字节码编译器： Java 源码 → JVM 字节码 (javac)，或 JavaScript → V8 字节码 (Ignition)
2. The Raw Material: Inside a Bitcell
2. 原材料：位单元（Bitcell）内部
The fundamental building block of any SRAM (Static Random-Access Memory) is the bitcell — a tiny circuit that holds one bit. Hardware teams design and characterize these cells by hand; the memory compiler’s job is to replicate them at scale. 任何 SRAM（静态随机存取存储器）的基本构建块都是位单元（bitcell）——一个存储一位数据的微小电路。硬件团队通过手工设计并表征这些单元；而内存编译器的任务就是大规模地复制它们。
The most common variant is the 6T bitcell (six transistors). Three signal lines connect it to the outside world: WL (Word Line — selects a row), BL (Bit Line), and BLB (Bit Line Bar, the complementary signal): 最常见的变体是 6T 位单元（六个晶体管）。三条信号线将其与外部世界连接：WL（字线——选择行）、BL（位线）和 BLB（位线反相，即互补信号）：
(Diagram omitted for brevity) (此处省略示意图)
Transistor count: 晶体管数量：
- INV_L: PMOS M3 + NMOS M1 = 2
- INV_R: PMOS M4 + NMOS M2 = 2
- Access transistors: M5, M6 = 2
- Total: 6 → “6T”
- 访问晶体管：M5, M6 = 2
- 总计：6 → “6T”
Positive Feedback: How a Bit Gets Locked 正反馈：位是如何被锁定的
Two inverters connected head-to-tail (cross-coupled): 两个首尾相连（交叉耦合）的反相器：
- Assume Q = 1 (high, Vdd)
- 假设 Q = 1（高电平，Vdd）
- INV_R receives 1, outputs 0 to Q’
- INV_R 接收到 1，向 Q’ 输出 0
- INV_L receives 0, outputs 1 back to Q
- INV_L 接收到 0，向 Q 输出 1
- Q stays 1 — a perfect closed loop
- Q 保持为 1 —— 一个完美的闭环
This is positive feedback + bistability. As long as Vdd is present, Q and Q’ are locked at opposite voltages indefinitely. The stored bit is literally just the voltage sitting on those two nodes. SRAM is called “Static” because — unlike DRAM — it never needs to refresh. 这就是正反馈加双稳态。只要 Vdd 存在，Q 和 Q’ 就会无限期地锁定在相反的电压上。存储的位实际上就是这两个节点上的电压。SRAM 被称为“静态”是因为它与 DRAM 不同，永远不需要刷新。
Three Operations 三种操作
- Hold (Standby): WL = 0, access transistors off. Cross-coupled inverters maintain state entirely on their own; only leakage current flows. Strictly speaking, Hold is a state, not an operation — but datasheets list it alongside Read/Write because designers need leakage current figures for power budgeting.
- 保持（待机）： WL = 0，访问晶体管关闭。交叉耦合的反相器完全靠自身维持状态；只有漏电流流过。严格来说，保持是一种状态而非操作——但数据手册将其与读/写并列，因为设计人员需要漏电流数据来进行功耗预算。
- Read: Precharge BL and BLB to Vdd. Assert WL high; M5 and M6 turn on. The side storing 0 pulls its bitline down by ~100 mV. Sense amplifier amplifies the small differential → 1 bit out.
- 读取： 将 BL 和 BLB 预充电至 Vdd。将 WL 置高；M5 和 M6 导通。存储 0 的一侧将其位线拉低约 100 mV。灵敏放大器放大微小的差分信号 → 输出 1 位数据。
- Read Disturbance: the moment WL turns on, the high-voltage BLB can pull up Q’ (the node storing 0) slightly through M6. If it rises past the switching threshold of INV_L, the cell flips — a Destructive Read. The fix is making the pull-down NMOS M2 stronger (wider) than the access transistor M6. This strength ratio is the Beta Ratio (β = W_pull-down / W_access), typically required to be > 1. This is why the six transistors in a standard bitcell are not all the same size.
- 读取干扰： 当 WL 开启的瞬间，高电压的 BLB 可能通过 M6 将 Q’（存储 0 的节点）稍微拉高。如果它超过了 INV_L 的开关阈值，单元就会翻转——这就是破坏性读取。解决方法是使下拉 NMOS M2 比访问晶体管 M6 更强（更宽）。这种强度比称为 Beta 比（β = W_下拉 / W_访问），通常要求 > 1。这就是为什么标准位单元中的六个晶体管尺寸并不完全相同。
- Write: Write driver forces BL and BLB to target values (one high, one low). Assert WL high. Write driver strength overcomes the cell’s pull-up → forces the cell to flip. The sizing trade-off between these forces is called the pull-up ratio.
- 写入： 写入驱动器强制 BL 和 BLB 达到目标值（一个高，一个低）。将 WL 置高。写入驱动器的强度克服单元的上拉能力 → 强制单元翻转。这些力之间的尺寸权衡称为上拉比。
Beyond 6T: Other Bitcell Types 超越 6T：其他位单元类型
6T is not the only option. Different use cases demand different trade-offs: 6T 并不是唯一的选择。不同的用例需要不同的权衡：
| Cell | Transistors | Key property | Typical use |
|---|---|---|---|
| 6T | 6 | High density, standard read/write | L2/L3 caches |
| 8T | 8 | Isolated read port, no read disturb | L1 caches, register files |
| 10T | 10 | Ultra-low voltage operation | Near-threshold designs |
| 单元 | 晶体管 | 关键特性 | 典型用途 |
|---|---|---|---|
| 6T | 6 | 高密度，标准读/写 | L2/L3 缓存 |
| 8T | 8 | 隔离读端口，无读取干扰 | L1 缓存，寄存器堆 |
| 10T | 10 | 超低电压操作 | 近阈值设计 |
The 8T cell adds a dedicated read path (two extra transistors) so the read operation never touches the storage nodes — eliminating read disturbance entirely at the cost of ~33% more area. 8T 单元增加了一条专用读取路径（额外两个晶体管），因此读取操作永远不会触及存储节点——以增加约 33% 的面积为代价，彻底消除了读取干扰。
3. Why a Memory Compiler Exists
3. 为什么需要内存编译器
When a hardware team designs an SoC (System on Chip), they need SRAM — lots of it, at many different sizes. The fundamental unit they work with is a cell: the smallest verified building block of an SRAM array. But a chip might need an SRAM of depth 512 × width 32 in one place, and depth 4096 × width 64 in another. Redesigning a new cell from scratch for every configuration is not feasible. 当硬件团队设计 SoC（片上系统）时，他们需要 SRAM——而且是大量、多种尺寸的 SRAM。他们使用的基本单元是 cell：SRAM 阵列中最小的已验证构建块。但芯片可能在某处需要 512 深 × 32 宽的 SRAM，而在另一处需要 4096 深 × 64 宽的 SRAM。为每种配置从头重新设计一个新单元是不可行的。
The solution is a parameterized IP: instead of a fixed design, you ship a tool that accepts parameters and generates the correct implementation automatically. That tool is the memory compiler. 解决方案是参数化 IP：与其提供固定设计，不如提供一个接受参数并自动生成正确实现的工具。这个工具就是内存编译器。
Given depth, width, port count, and a few other knobs, it produces a complete, tapeout-ready SRAM macro. A memory compiler generates a complete, self-contained SRAM macro — the bitcell array plus all the peripheral circuitry needed to operate it: row/column decoders, sense amplifiers, write drivers, and self-timed control. 给定深度、宽度、端口数量和其他一些调节旋钮，它就能生成一个完整的、可流片的 SRAM 宏单元。内存编译器生成的是一个完整、自包含的 SRAM 宏——包括位单元阵列以及操作它所需的所有外围电路：行/列解码器、灵敏放大器、写入驱动器和自定时控制逻辑。
What it does not generate is the memory controller — the system-level logic that decides what to read and write, handles arbitration and BIST sequencing, and lives in the SoC RTL outside the macro. 它不生成的是内存控制器——即决定读写内容、处理仲裁和 BIST 序列的系统级逻辑，这些逻辑位于宏单元之外的 SoC RTL 中。