First CHERIoT Silicon

首款 CHERIoT 芯片问世

Most CHERIoT work to date has been done on software or FPGA simulations. We have several such implementations: The executable model built from our formal ISA specification, the MPact simulator from Google, Microsoft’s CHERIoT SAFE FPGA target for the Arty A7, and of course lowRISC’s beautiful Sonata FPGA board, which is designed to simulate CHERIoT systems. 迄今为止，大多数 CHERIoT 的相关工作都是在软件或 FPGA 仿真环境下完成的。我们已经拥有了几种此类实现：基于我们正式 ISA 规范构建的可执行模型、Google 的 MPact 模拟器、微软为 Arty A7 开发的 CHERIoT SAFE FPGA 目标板，当然还有 lowRISC 出色的 Sonata FPGA 开发板，它专为模拟 CHERIoT 系统而设计。

These were always intended to be developing and prototyping systems, so I’m delighted to announce that SCI Semiconductor has the first silicon CHERIoT implementation. [ Conflict disclaimer: I am a co-founder of SCI Semiconductor. ] 这些系统一直以来都被定位为开发和原型设计平台，因此我很高兴地宣布，SCI Semiconductor 已经实现了首款 CHERIoT 硅片。[利益冲突声明：我是 SCI Semiconductor 的联合创始人。]

The dev board pictured above contains one of the first batch of ICENI chips to come back from the fab. This is a complete CHERIoT system, with all of the core CHERI properties (spatial memory safety, no pointer injection, and so on) along with all of the CHERIoT extensions that provide deterministic use-after-free protection, auditable control over interrupt state, and everything that we need for an aggressively compartmentalised RTOS. 上图所示的开发板搭载了首批从晶圆厂回片的 ICENI 芯片。这是一个完整的 CHERIoT 系统，具备所有核心 CHERI 特性（空间内存安全、无指针注入等），以及所有 CHERIoT 扩展功能，这些扩展提供了确定性的“释放后使用”（use-after-free）保护、可审计的中断状态控制，以及我们构建激进分区式实时操作系统（RTOS）所需的一切功能。

This chip uses the CHERIoT Ibex core, running at up to 250 MHz, and includes a few feature that accelerate temporal safety, improve interrupt determinism, and so on. These build on top of all of the benefits of any CHERIoT implementation: deterministic mitigation of memory safety bugs from simple buffer overflows up to use-after-free, fine-grained compartmentalisation, and a programming model co-designed with both the ISA and the software stack to provide a tiny TCB. 该芯片采用 CHERIoT Ibex 内核，运行频率高达 250 MHz，并包含一些加速时间安全性、改善中断确定性等特性的功能。这些功能建立在所有 CHERIoT 实现的优势之上：从简单的缓冲区溢出到“释放后使用”，对内存安全漏洞进行确定性的缓解；实现细粒度的分区；以及与 ISA 和软件栈共同设计的编程模型，从而提供极小的可信计算基（TCB）。

Anything that works on CHERIoT SAFE or Sonata should be very easy to port to ICENI for production use. Anything that runs on the software simulators should just work. 任何能在 CHERIoT SAFE 或 Sonata 上运行的程序，都可以非常轻松地移植到 ICENI 上进行生产使用。任何能在软件模拟器上运行的程序也应该可以直接运行。

We’ll be showing the chips at Embedded World (Stand 4A - 131) next week and at CHERI Blossoms a couple of weeks later. From tomorrow, one will also be on display in the CHERI 15th anniversary exhibit in the Cambridge Computer Laboratory. 下周我们将在 Embedded World（展位 4A - 131）展示这些芯片，几周后还将在 CHERI Blossoms 活动上展出。从明天开始，其中一块芯片也将在剑桥大学计算机实验室的 CHERI 15 周年展览中展出。

Aside: The Iceni tribe were one of the pre-Roman tribes in Britain and are famous for their chariots (though more due to this statue than historical fact). I am only partially to blame for the bad puns in the naming. 题外话：爱西尼（Iceni）部落是罗马统治前英国的部落之一，以其战车（chariots）而闻名（尽管这更多归功于这座雕像，而非历史事实）。对于命名中这些糟糕的双关语，我只负部分责任。