RISC-V: They Should Have Known Better
RISC-V: They Should Have Known Better
RISC-V：他们本该做得更好
I am often asked to explain my distaste for RISC-V and I often find myself explaining it piecewise. The reactions are often of the form “you just do not understand the brilliance of it all”, which is, of course, no argument at all. After being asked for the Nth time to explain, I decided to put it all down in one place so that I could simply link to it when asked next. Plus, if anyone wishes, then, to form a coherent counter-argument, they could refer to my points clearly and in detail by having this text as a reference. All opinions stated here are mine and do not represent the views of my employer, any deity, or my landlord. My cats concurred in part and dissented in part and will publish their opinion later.
我经常被问到为什么对 RISC-V 感到反感，而我往往只能零碎地进行解释。人们的反应通常是“你只是不理解它的精妙之处”，这当然根本算不上什么论据。在第 N 次被要求解释后，我决定把所有观点整理在一起，这样下次再被问到时，我只需发送链接即可。此外，如果有人希望提出连贯的反驳意见，他们也可以通过参考本文，清晰且详细地针对我的观点进行回应。文中所有观点仅代表我个人，不代表我的雇主、任何神灵或房东的立场。我的猫对此部分赞同、部分反对，并将在稍后发表它们的看法。
Everything for Everyone
面向所有人的万能方案
RISC-V will own the cheap-as-dirt single-use microcontroller space eventually. Not due to its ISA design, but despite it. The first and simplest-to-grasp issue is that one cannot be best for all use cases. RISC-V fans would have you believe that RISC-V will soon own all supercomputers, while also owning all the tiny microcontroller use cases, and all things in between. This is impossible, and would be equally impossible for any ISA. Simply put, the things a high-end CPU needs are diametrically opposed to the things a small cost-saving microcontroller core needs. The design choices are not merely microarchitectural, but actually (and necessarily) impact the CPU architecture itself.
RISC-V 最终会占领廉价的一次性微控制器市场。这并非因为其指令集架构（ISA）设计出色，恰恰相反，是因为它克服了设计上的缺陷。第一个最容易理解的问题是：没有任何架构能同时在所有应用场景中做到最好。RISC-V 的拥趸们试图让你相信，RISC-V 很快将统治所有超级计算机，同时还要统治所有微型微控制器应用场景，以及介于两者之间的所有领域。这不仅是不可能的，对于任何 ISA 来说也同样不可能。简单来说，高端 CPU 所需的特性与小型低成本微控制器核心所需的特性是截然相反的。这些设计选择不仅仅是微架构层面的，实际上（且必然地）会影响到 CPU 架构本身。
For what it is worth, I am 100% sure that RISC-V will own the cheap-as-dirt single-use microcontroller space eventually. Not due to its ISA design, but despite it. It will take this role from 8051 by being an improvement on it — a bar so low, it is but a speed bump. What does a cheap microcontroller core need? Let’s inspect what they are used for. Typical use cases are to interface with and quickly reconfigure hardware blocks in a larger chip, eg in an MP3 player, an SD card, or a USB stick. The hard work is done by custom IP and the CPU core is just there to occasionally prod a register or configure something.
无论如何，我百分之百确定 RISC-V 最终会占领廉价的一次性微控制器市场。这并非因为其 ISA 设计，而是尽管有其设计缺陷。它将通过改进 8051 来取代其地位——这个门槛低到几乎可以忽略不计。廉价微控制器核心需要什么？让我们看看它们的用途。典型的应用场景是与大型芯片中的硬件模块进行接口并快速重新配置，例如在 MP3 播放器、SD 卡或 USB 闪存盘中。繁重的工作由定制 IP 完成，而 CPU 核心只是偶尔触碰一下寄存器或进行一些配置。
What matters in this case is interrupt latency (lower is better) and size (smaller is better). Usually you would not expect much math to be done on such a core. Mass-produced cost-reduced devices would have the code running out of real ROM (if non-updateable) or RAM (if updateable); NOR flash costs too much and is not an option for really-mass-produced things. When running out of ROM, code size matters because ROMs are not very compact. When running out of RAM, code size matters because SRAMs also take up a lot of space on the die. Thus, code density matters for these use cases. Since much math is not expected, things like hardware dividers (or even multipliers) can be discarded. Privilege separation is also not needed in such single-use situations — no external untrusted code is expected to ever be fetched.
在这种情况下，重要的是中断延迟（越低越好）和尺寸（越小越好）。通常你不会指望这种核心进行大量的数学运算。大规模生产的低成本设备代码通常运行在真正的 ROM（如果不可更新）或 RAM（如果可更新）中；NOR Flash 成本太高，对于真正大规模生产的产品来说不是一个选择。当从 ROM 运行时，代码大小很重要，因为 ROM 并不紧凑。当从 RAM 运行时，代码大小也很重要，因为 SRAM 在芯片上也占用大量空间。因此，代码密度对于这些应用场景至关重要。由于不需要进行大量数学运算，硬件除法器（甚至乘法器）等组件都可以舍弃。在这种单用途场景下，也不需要权限隔离——因为预计不会有外部不可信代码被加载。
“But,” you might say, “you just described RV32IC (or RV32EC)!” So, at basically the only purpose such an embedded core has, RISC-V is notably worse than the leading existing competitor. Indeed, it is somewhat close, except really you need RV32I_Zicsr to claim that. Without Zicsr, there is no spec-compliant way to handle interrupts, as there is no temporary place to stash a register to allow you to stash the rest of them. MIPS reserved two kegs for this ($k0 and $k1). Without them, RISC-V needs mscratch/sscratch. Without Zicsr, you do not have those and are stuck with weird other methods to do things. And thus we are back in 8051 territory - it specializes in doing things weirdly.
“但是，”你可能会说，“你刚才描述的不就是 RV32IC（或 RV32EC）吗！”所以，在嵌入式核心几乎唯一的用途上，RISC-V 明显不如现有的领先竞争对手。确实，它在某种程度上很接近，但前提是你必须拥有 RV32I_Zicsr 扩展。如果没有 Zicsr，就没有符合规范的中断处理方式，因为没有临时空间来暂存寄存器，从而无法保存其余寄存器。MIPS 为此预留了两个寄存器（$k0 和 $k1）。没有它们，RISC-V 就需要 mscratch/sscratch。而没有 Zicsr，你就没有这些寄存器，只能被迫使用其他奇怪的方法来处理。于是我们又回到了 8051 的领域——它擅长以奇怪的方式做事。